1. Field of the Invention
The present invention relates to a method for fabricating a thin film transistor. More particularly, the present invention relates to a method for fabricating a thin film transistor having a double metal layer and a fine source/drain dimension using a highly conductive metal.
2. Description of the Related Art
With the rapid development of opto-electronic technologies, digital video and imaging devices have become some of the most common electrical appliances in our daily life. One of the most important man-machine communication interfaces for the digital video or imaging device is the display. A user can easily read information from the display to perform controlling operations.
Thin film transistor (TFT) is a driving device commonly deployed inside a display. Typically, the thin film transistor comprises a gate, a channel and a source/drain. In recent years, the process of forming the source/drain includes depositing a plurality of metallic layers (for example, chromium/aluminum/chromium composite layer or a molybdenum/aluminum/molybdenum composite layer) and performing a wet etching process to pattern the multi-layered metallic layer. However, with the continuous reduction of line widths, a source/drain interconnection using the aforementioned materials often leads to an increase in the resistor-capacitor (RC) delay that the operating speed of the thin film transistor will be slowed down. Thus, using a metallic material with good electrical conductivity to form the source/drain interconnect can minimize the RC delay effect significantly.
Due to the high electrical conductivity, interconnection using copper wires will be a major trend in the future. Yet, the fabrication of copper wires has a few problems: (1) it is difficult to control the dimension of copper patterns in a wet etching operation, and yet, it is hard to etch copper in a dry etching operation; (2) copper ions are easily diffused into surrounding areas leading to a change in the electrical properties of channel layers and/or the contamination of equipment. As a result, copper is often combined with other metals (for example, molybdenum) to form a multi-layered metallic layer in the fabrication of the source/drain.
FIG. 1 is a schematic cross-sectional view of a conventional thin film transistor having a source/drain fabricated using a molybdenum/copper/molybdenum multi-layered metallic layer. As shown in FIG. 1, the thin film transistor 100 comprises a substrate 110, a gate 120, a gate-insulating layer 130, a semiconductor layer 140 and a pair of source/drain 150. The semiconductor layer 140 comprises a channel layer 142 and an ohmic contact layer 144 and the source/drain 150 comprises a molybdenum layer 152, a copper layer 154 and another molybdenum layer 156.
To form the source/drain 150, a patterned photoresist layer 160 is formed over the thin film transistor 100. Then, using the patterned photoresist layer 160 as a mask, a wet etching of the underlying molybdenum layer 156 and the copper layer 154 is carried out. However, because copper has an etching rate greater than molybdenum, the effect of side undercuts 170 is occurred in the wet etching operation as shown in FIG. 1. Thus, the possibility of forming a line cut or a thin film transistor 100 that does not match the dimensional specifications is increased. Furthermore, since the copper layer 154 is dipped inside a pool of etching solution in the wet etching operation, copper ions may diffuse into the nearby semiconductor layer 140 by hitching a ride with the etching solution. Ultimately, the electrical performance of the thin film transistor 100 is affected.
Furthermore, after performing the wet etching operation, a dry etching operation is carried out to remove the molybdenum layer 152 above the gate 120 and a back channel etching (BCE) operation is carried out to remove the ohmic contact layer 144 and a portion of the channel layer 142 above the gate 120.
FIG. 2 is a schematic cross-sectional view showing the dry etching operation for removing the molybdenum layer above the gate and the back channel etching operation. In the dry etching operation, the copper atoms can diffuse into areas in the neighborhood of the semiconductor layer 140 and affect the electrical properties of the semiconductor layer 140 because the copper layer 154 is still exposed in the etching environment. Moreover, since the patterned photoresist layer 160 still serves as a mask in the dry etching operation and the back channel etching operation, a side surface 180 of the molybdenum layer 152, the ohmic contact layer 144 and the channel layer 142 aligns with the edge of the patterned photoresist layer 160. It should be noted that there is a large difference in the dimension between the side surface 180 of the molybdenum layer 152 and the side undercut 170 of the copper layer 154. This causes an unfavorable condition for forming a source/drain 150 with a fine dimension.